1. Field of the Invention
The present invention relates to the field of miniaturized electronic components.
2. Description of the Related Art
In the field of voltage controlled integrated electronic components, currently MOS (Metal-Oxide-Semiconductor) type transistors are most commonly used, in which an isolated gate is positioned above a semiconductor portion in which a conducting or non-conducting channel can be formed depending on the biasing of the gate. A distinction is generally made between MOS transistors formed on a semiconductor wafer and MOS transistors formed on a thin semiconducting layer covered by an insulating layer mounted on a silicon wafer (SOI structure).
All of these MOS transistors present diverse problems when it is attempted to reduce their dimensions in order to achieve sizes in the order of several tens of nanometers. Among these problems, there are in particular the following:                particular effects known as short channel effects are produced, these effects resulting in only partial control of the channel inversion caused by the field of the gate; this notably results in dependencies between the threshold voltage of the transistor, the length of the gate and the voltage applied between the source and drain of the transistor;        it is difficult to obtain a gate oxide sufficiently thin and this leads to the use of gate insulating materials having very high dielectric constants which today cause integration problems;        the cost of SOI type structures is currently very high;        there are difficulties, in particular when a CMOS structure is used, in other words an N-channel MOS transistor positioned alongside a P-channel MOS transistor, to achieve good isolation between the transistors. Currently, the most common technique consists in using shallow isolation trenches (STI or Shallow Trench Isolation) or using insulating SOI wells, which lead to insulating surfaces between the transistors which have approximately the same surface area as the transistors, thereby resulting in a large area of lost space on the semiconductor chip;        in general, there are numerous problems in differentiating between the ON and OFF states.        